1. Technical Field of the Present Invention
The present invention generally relates to phase locked loop systems, and more particularly, to methods and apparatuses that use derivative control in such phase locked loop systems.
2. Description of Related Art
Recent advances in integrated circuit manufacturing technology have allowed the number of transistors to increase on single integrated circuit chips, and increased the performance of the transistors. This is especially noticeable in high density synchronous circuits, such as microprocessors, math co-processors, single-chip microcomputers, and the like. This higher performance is typically obtained from synchronous circuits by increasing the frequency of the clock signal controlling the circuit.
Particularly at extremely high clock frequencies, parasitic impedances, propagation delays, and other effects, can cause the clock signals that are applied to different integrated circuits within a computer system to be skewed in time relative one to another. As a result, inter-chip communication within such computers is made more difficult at higher frequencies, thus, requiring wait states or other techniques to be used to reliably communicate the data The synchronization of multiple chips often tends to degrade the rate at which data can be communicated within the system, and thus degrade over all system performance. In addition, high frequency clock signals are especially vulnerable to certain instabilities in their duty cycle to noise, ringing, and other similar effects that may cause errors in the internal operation of the integrated circuits receiving such signals.
Phase-Locked Loops (PLLs) are conventionally implemented on integrated circuits to overcome these problems. A typical PLL includes a phase detector circuit, a low pass loop filter, and a voltage controlled oscillator (VCO). The phase detector circuit compares the phase of the input clock signal with the output of the VCO, and provides a control voltage to the VCO (after filtering by the loop filter) to adjust the frequency of the output signal. After several cycles, the PLL locks onto the input clock signal, and provides an output having a stable frequency and phase. A frequency divider may also be connected to the output of the VCO to provide an output clock at frequency different from the VCO frequency.
These traditional PLLs are implemented using an integral and a proportional control. Although such control may be suitable for some applications, it would be further desirable to have an additional control that would take into account the rate of change at which the errors are occurring (derivative). It would be further advantageous if the derivative control could be used in addition to the integral and proportional control. The present invention teaches such a combined integral, proportional, and derivative control PLL system.